The invention is directed to a digital phase locked loop for controlling frequency and phase of an output clock signal dependent on a reference signal.
Current and future digital communication networks are largely transparent in view of the data transmission rates that are employed and also enable the use of different transmission methods or transmission protocols for the transmission of digital informationxe2x80x94for example, synchronous digital hierarchy (SDH), plesiochronic digital hierarchy (PDH) and gigabit Ethernet. In such digital communication networks, it is necessary to provide devices for data regeneration or for restoring the amplitude, signal edge and clock of the communicated, digital data stream.
Digital phase locked loops are known for this purpose, these being utilized for clock recovery or for generating a clock signal from the transmitted, digital data stream. Such digital phase locked loops usually comprise analog or digital voltage-controlled oscillators for generating an output clock signal, digital frequency dividers and phase or frequency discriminators for comparing the output clock signal to an external reference signal. The function of such digital phase locked loops for recovering the clock from a digital data stream is adequately known to a person skilled in the art, so that their functioning shall not be discussed in greater detail.
Further, it is particularly required for digital signal multiplex devices within digital communication networks to support a plurality of different transmission methods or different transmission protocolsxe2x80x94for example, synchronous digital hierarchy (SDH) and plesiochronic digital hierarchy (PDH) xe2x80x94,i.e. to be able to recover the data from the transmitted, digital data stream regardless of the transmission protocol or the transmission rate with which the data were transmitted. Interfaces that support both the SDH protocol with a transmission rate of 155.52 MHz as well as the PDH protocol with a lower transmission rate of 139.149 MHz or can be operated in the SDH or PDH mode must therefore be provided on such digital signal multiplex devices. For this purpose, such switchable interface modules usually comprise at least two analog, PLLs, whereby the one PLL is operated in the SDH mode and the other PLL is operated in the PDH mode, and switching between the two PLLs is undertaken dependent on the incoming digital data or, respectively, the data stream.
For clock recovery of different demultiplexed channels of the digital data stream, additionally a clock signal that matches the data of the respective demultiplexed channel must be recovered. Thus, the transmission rate or the gap timing signal of the different channels recovered by demultiplexing the incoming digital data stream can deviate slightly from the transmission rate or from the transmission clock of the communication system, or the recovered clock signal can exhibit phase fluctuations (jitter). The data separated according to channels together with their gap timing signal are read into a buffer memory and are intermediately stored before further transmission to the communication system. For reading out the data separated according to channels, a digital phase locked loop PLL is respectively utilized per channel for generating a stable and low-jitter clock signal. For this purpose, additional high-quality phase locked loops are needed due to the demand made of the jitter attenuation.
An object of the invention is to specify a digital phase locked loop for different frequency bands respectively having a plurality of selectable phases. Proceeding from a digital phase locked loop, this object is achieved wherein a digital phase locked loop is provided for controlling frequency and phase of an output clock signal dependent on a reference signal. A ring oscillator is provided for generating the output clock signal and is formed of a switchover unit and of a plurality of serially arranged delay units. A phase comparator compares a phase of the reference signal and of the output clock signal. At least one switchable frequency divider unit is provided. A control unit controls a frequency of the ring oscillator by cut-in or cut-out of delay units with assistance of a switchover unit.
This object is achieved by a digital phase locked loop for controlling frequency and phase of an output clock signal dependent on a reference signal that comprises a ring oscillator for generating the output clock signal that is formed of a switchover unit and a plurality of serially arranged delay units and comprises a phase comparator for comparing the phase of the reference signal and the output clock signal. Further, the digital phase locked loop comprises at least one switchable frequency divider unit and a control unit for regulating the ring oscillator frequency by activating or deactivating delay units with the assistance of the switchover unit. As a result thereof, a ring oscillator is especially advantageously realized digitally with the assistance of a plurality of delay units, whereby the outputs of the delay units are connected to the inputs of the switchover unit, i.e. the return of the ring oscillator is switchable. As a result of the cut-in or cut-out of one or more delay units, the ring oscillator frequency can be individually regulated with the assistance of the switchover unit and of the control unit. Given a fixed plurality of serially connected delay units of the ring oscillator, output clock signals respectively comprising the same frequency advantageously pend at the outputs of the delay units, whereby these output clock signals exhibit different phase positions. All phase positions of the output clock signal can thus be taken at the respective outputs of the delay units with the assistance of the switchover unit. The digital phase locked loop can be realized cost-beneficially and in resource-saving fashion in a purely digital way, for example in an ASIC (application-specific integrated circuit), as a result whereof the provision of an external oscillator is eliminated. The xe2x80x9clayoutingxe2x80x9d of the electronic circuit is thus particularly advantageously simplified as a result of the low number of electronic components, the noise emission is reduced, and a higher packing density of the individual interfaces per module is enabled.
A further critical advantage of the invention is that a further switchover unit is provided for generating a recovered output clock signal with slightly different phase position and frequency compared to the output clock signal. This is accomplished by continuously cyclically taking the signals respectively comprising a different phase present at the outputs of the delay units of the ring oscillator. Advantageously , a recovered output clock signal wit h slightly different phase and frequency compared to the output clock signal is inventively acquired by a further switchover unit. For example, the buffer memory of an input interface module of a digital multiplexer is written or read with the assistance of this recovered, stable and low-jitter output clock signal. As a result of the provision according to the invention of a further switchover unit of, for example a digitally realized multiplexer, the output clock signals of a plurality of channels that exhibit a different frequency offset with respect to the reference signal can be recovered and used for the readout of the respective buffer memory. As a result of the inventive combination of a multiplexer and a digital ring oscillator, the plurality of phase locked loops needed for the clock recovery of the individual transmission channels is reduced to nearly a single digital phase locked loop that comprises a plurality of inventive xe2x80x9coutfeed unitsxe2x80x9d or switchover units. Additionally, the generation of the output clock signal and the clock recovery of a recovered output clock signal exhibiting a slight frequency difference with respect to the output clock signal is decoupled.
According to a further development of the invention, at least one phase comparator an d at least one switchable frequency divider unit inserted between the ring oscillator and the phase comparator are provided, so that output clock signals can be generated with different frequencies. With the assistance of the switchable frequency divider unit, it is advantageously possible to generate frequencies within the frequency interval defined by two neighboring delay units. This is accomplished by a cyclical switching in a defined relationship between the signal at the output of the one delay unit and the signal at the output of the neighboring delay unit. By regularly taking the signals at the outputs of neighboring delay units and respectively exhibiting a different phase, output clock signals having intermediate frequencies between the characteristic frequencies of the ring oscillator can be generated. Thus selection of the signal to be taken is implemented according to the criterion of the xe2x80x9cBresenhamxe2x80x9d algorithm known from computer graphics.
Another critical advantage of the phase locked loop of the invention is that the frequency divider unit comprises a first and a second divider counter. The counter reading of the first divider counter determines the number of clock periods for an output clock signal exhibiting a first frequency. The counter reading of the second divider counter determines the number of corresponding clock periods for an output clock signal exhibiting a second, neighboring frequency. An output clock signal having a frequency lying between a first and a second, neighboring frequency can be generated on the basis of the counter readings of the first and second divider counters. Advantageously, output clock signals having a frequency that lies between the frequencies of the output clock signals that can be taken from the ring oscillator can also be generated with the assistance of the first and second divider counter provided in the frequency divider unit.
According to a further development of the invention, a first and a second counter are provided. The first counter is started with a first, whole-number start value N1 and the second counter is started with a second whole-number start value N2 by a signal edge of the reference signal. The ratio of the first to the second start value N1/N2 is determined by the required relationship of the output clock signal to the reference signal. Based on the sequence of the run-down of the first and second counters, a first control signal is generated by the switch-over unit for the cut-in or cut-out of delay units within the ring oscillator. By employing first and second counters which, for example, are started with the leading edge of the reference signal, the frequency of the output clock signal is advantageously approximated to the frequency of the reference signal. Thus a further delay unit is cut-in or cut-out by the switchover unit with the assistance of the first control signal generated by the control unit and dependent on which counter ran down first. This approximation is implemented until the divided ring oscillator frequency coincides with the divided frequency of the reference signal except for a slight frequency difference.
According to a further development of the invention, a third and fourth circular counter are provided. The third circular counter is started with a third, whole-number start value N3 and the fourth circular counter is started with a fourth whole-number start value N4 by a signal edge of the reference signal. The counter reading of the third counter is reduced by a count unit with a respective clock edge of the divided reference signal. The counter reading of the fourth counter is respectively reduced by a count unit with a clock edge of the divided output clock signal. Further, the ratio of the third and fourth start value N3/N4 is defined by the required relationship of the reference signal to the output clock signal. The counter reading of the third and fourth circular counter are compared at a zero-axis crossing of the third or fourth counter. The counter reading of the first and/or second divider counter is incremented or deincremented on the basis of the comparison result. As a result thereof, a xe2x80x9cfine controlxe2x80x9d of the output signal can be especially advantageously realized in view of the reference signal, whereby the xe2x80x9cfine controlxe2x80x9d of the digital phase locked loop is implemented nearly uninterrupted in the steady state.
A further aspect of the invention is that the further switch-over unit respectively through-connects a recovered output signal with a defined clock phase and frequency with the assistance of a second control signal generated by the control unit, and the second control signal is represented by a register value. Further, the register value is formed by a synchronous counter clocked by the reference signal and, for raising or lowering the clock phase and frequency of the recovered output clock signal, the synchronous counter is incremented or deincremented by respective, predetermined whole-number value. The predetermined, whole-number increment value is thus provided for offset formation between reference signal and recovered output clock signal. As a result thereof, output clock signals that exhibits a fixed or adjustable offset with respect to the reference signal can be generated in an especially simple way. For example, the data upon readout of a buffer memory of an input unit of a transmission system must be readout with nearly the same clock with which they were read into the buffer memory. The regeneration of such a clock from the incoming data stream or, respectively, data signals is substantially simplified by the application of the invention due to the different phase positions of the output clock signal already present in the ring oscillator, i.e. the inventive regeneration can be realized without substantial, circuit-oriented outlay, particularly without providing an additional, analog oscillator.
The invention is explained in detail below on the basis of preferred exemplary embodiments with reference to the drawing figures.